The invention relates to a programmable logic array employing electrically erasable array switches and dual purpose programming circuitry for programming both arrays of the device, and to an improved technique for testing programmable logic arrays employing electrically erasable array cells.
The conventional field programmable logic array comprises two separate arrays. The logic function performed by the two arrays is "AND OR" logic, and therefore it is conventional to designate the respective arrays as the AND array and the OR array.
The AND array is conventionally arranged as a matrix of rows coupled to input lines and columns. Each input line may selectively be connected to a column (depending on the desired logic architecture) by programming a switch in the AND array to the conductive state. Conventional devices employ bipolar technology with the switches comprising fuses or links which are selectively blown by passing a high current level and are therefore one-time programmable devices.
The preferred method of constructing an array of metal-oxide-semiconductor (MOS) devices is with a common drain, as opposed to a stack with sources and drains connected in series. Therefore, to use the common drain transistor implementation for both the AND and OR arrays, DeMorgan's theorem is applied to achieve the desired "AND OR" logic. Thus, by inverting the AND outputs (the "product terms"), as well as the AND array inputs, "AND OR" logic may be implemented with two arrays configured as OR gates. This implementation is referred to as "invert OR-invert OR" logic.
The inverters located between the arrays serve a logical function, to achieve the "AND OR" logic, and also acts as a buffer between the product term and the OR array row. The buffer characteristic of this inversion stage makes the programming of the OR array in "invert OR-invert OR" implementation more cumbersome than in an "invert OR AND" array implementation or a true "AND OR" implementation of a programmable logic array. The difficulty arises from the fact that, because of the inverters, the high voltage used to program the columns of the AND array cannot be directly placed on the rows of the OR array. Thus, separate row address decoding circuits are respectively provided for the programming of the AND array and the OR array.
As programmable logic arrays become larger, testing of the device becomes more complex and time consuming. For devices employing electrically erasable cells, the time required to program the cells is typically a large component of test time.
It would therefore represent an advance in the art to provide a programmable logic array which employs electrically erasable cells in the AND and OR arrays to provide a reconfigurable logic array.
It would also be advantageous to provide a programmable logic array with dual purpose programming circuitry for programming both the AND and OR arrays to conserve die area.
Another object of the invention is to provide an improved technique for testing programmable logic arrays employing electrically erasable cells to minimize testing time.